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How to read/write file in host when running Verilog code in a development board?

zzzhhh

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We know that Verilog has file I/O system task functuons. But in practical FPGA development on a development board connected to host PC with a micro-USB cable, say, a Xilinx Artix-7 board, how to read/write file in host PC when simulating Verilog code on the board using Vivado 2022.2? Thanks.
 
"Simulating Verilog code on the development board" is self-contradictory, you either run the code on the target FPGA or simulate it on the PC.

Presume you mean running the code on the FPGA, then you can't use Verilog file I/O, it's only a simulation feature. Data in- and output from your FPGA application can be performed through hardware communication channels, e.g. serial interface or ethernet, to a limited extent also through JTAG adapter and Vivado debug tools.
 

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