Regarding Negative edge D flip flop with synchronous active low set

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Abdul mohsin

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Negative edge D flip flop with synchronous active low set

can any one draw the circuit of Negative edge dff with synchronous active low set ..actually i draw the circuit but am getting the wrong outputs by using the tool..so can any one suggest r any link for this cell....
 

i was about to do this for you but i did mine using pass logic, i expect you want full cmos...

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Ok had to go back to the good ole basic cmos digital book, i work more in the realm of analog. but it seems pretty simple to me, if you take a normal negative edge triggered dff made of 2 dlatches, simply break the internal net that connects the 1st dlatch Q to the 2nd dlatch D, insert an and2, make the other and2 input your clrb(clr via inverter). this will make clear bit do nothing until clk goes to 0, at this point the output will be set to 0.
 

I drawn this circuit would u please suggest me,which book i hav to refer can u give me guidence...am attaching file.check once
 

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  • Dflop_with_synchronous low_set_Schematic.jpg
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Here is a quick barely readable scribble


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Opps i just realized you wanted an active low set, not a reset,

to convert use a nand.
 
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is it correct brother? am sending as screenshot plz go through it?
 

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  • Neg edge dff with synchronous active low set.png
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Yes that works but replace your OR with a NAND, tap off Qb instead of Q and rust Set straight to the nand, this will save 2 inverters.
 



Am Abdul regarding Neg edge Dff Synchronous with Active low set.I already send about this cell. But am getting wrong output it is working as latch...can u please give suggestion brot.I am sending screen shot please reply me brother.

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Am Abdul regarding Neg edge Dff Synchronous with Active low set.I already send about this cell. But am getting wrong output it is working as latch...can u please give suggestion brot.I am sending screen shot please reply me brother.
 

can you show circuit that you are using for this as well?

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Is hard to believe this is the same circuit, you are showing the output of a d latch changing while the clock is being held constant... is suspicious
-Pb
 

regarding negative edge dff synchronous with active low set
 

You drew the correct schematic, but the definition of a D latch is that when clock is low Q will not change, the question is why is your latch not working, I would try to verify the latch by itself. possibly you have miss wired in schematic? maybe something wrong with the delays ?
 




Is this circuit correct only na.K Actually i am not missed any wire brother . I am sending Screenshot which i drawn go through once.

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Is this circuit correct only na.K Actually i am not missed any wire brother . I am sending Screenshot which i drawn go through once.

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Is this circuit correct only na.K Actually i am not missed any wire brother . I am sending Screenshot which i drawn go through once.
 

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