polu
Newbie level 6
Hi,
I am having data flowing from a flop running at a higher frequency to a flop running at lower frequency. Its not a MCP. Let us say the time periods are Tx and Ty ( Tx < Ty)
I have an enable signal to allow the data transfer between theese flops. Say for every 'n' clocks once the data flow is stopped for a duration one clock cycle in order to avoid losing of launching data, as launching clock frequency is slightly higher than the capturing one. Which means PT need not to check the timing on that one perticular clock peroid for every 'n' clocks. Per say, the two (launch and capture) clock edges are 0.02 ns apart when the data transfer enable is deasserted. During the other cycles (when the datra transfer is asserted) the clock edges are seperated by morethan 0.02 say 1ns, 1.4 ns, 2ns, etc.
I want the timing check( setup) to happen on the edges seperated by 1ns. But not on the edges seperated by 0.02ns, as this is not a valid scenerio since there is no data transfer at that point. In other words I want the timing check to happen only when there is asserted enable.
Right now PT is looking for the least seperated edges i.e 0.02 and checking the timing on 0.02ns seperated edges and its failing, how can I excempt this check, so that the timing check happens on the correct edges (which are 1ns apart). Would like to remind you that this is not a multi cycle path.
Rgds.
I am having data flowing from a flop running at a higher frequency to a flop running at lower frequency. Its not a MCP. Let us say the time periods are Tx and Ty ( Tx < Ty)
I have an enable signal to allow the data transfer between theese flops. Say for every 'n' clocks once the data flow is stopped for a duration one clock cycle in order to avoid losing of launching data, as launching clock frequency is slightly higher than the capturing one. Which means PT need not to check the timing on that one perticular clock peroid for every 'n' clocks. Per say, the two (launch and capture) clock edges are 0.02 ns apart when the data transfer enable is deasserted. During the other cycles (when the datra transfer is asserted) the clock edges are seperated by morethan 0.02 say 1ns, 1.4 ns, 2ns, etc.
I want the timing check( setup) to happen on the edges seperated by 1ns. But not on the edges seperated by 0.02ns, as this is not a valid scenerio since there is no data transfer at that point. In other words I want the timing check to happen only when there is asserted enable.
Right now PT is looking for the least seperated edges i.e 0.02 and checking the timing on 0.02ns seperated edges and its failing, how can I excempt this check, so that the timing check happens on the correct edges (which are 1ns apart). Would like to remind you that this is not a multi cycle path.
Rgds.