echo47 said:I greatly improved the situation by applying LOC area constraints to each of my HDL modules. I also arranged the areas so the interconnecting signals were mostly short.
Please simply explain what is pipleline register and how to insert it?..I couldn't find any relevant doc in google. Thanks [/quote]echo47 said:A few signals still needed to jump across the chip, so I inserted a pipeline register into them to split the long propagation delay.
---Excellent "echo47"....You really deserve all credits...Anyway I'm not upto that level of excellency in FPGA design yet...I have not been through Manual routing yet...beginners like us need such helping hands from experts like you...continue your service..And one moreecho47 said:Here's an example that may help to clarify my description.
Let's say the FPGA does some sort of data processing using four HDL modules named A, B, C, and D. Data flows from the input pins through module A, then through module B, then through C, then through D, and finally out the output pins. If I don't apply any area constraints, ISE will dump all four modules into the middle of the chip and try to route them. Sometimes that works fine, but other times the congestion is too severe. To avoid the snarl, I constrain module A into the upper-left corner of the chip, module B into the upper-right corner, module C into the lower-right corner, and module D into the lower-left corner. I also try to place the input pins near module A, and the output pins near module D, to avoid long routes across the chip to the I/O pads. Now, when ISE routes the chip, there's much less routing congestion, and cleaner shorter routes between modules.
--Here What seems to be so advantageous in adding a D-flipflop?...For eg,a delay is a delay which can't be cut-down by anymeans once it's occured....So if we insert an D-FF,then the overhead is (Total delay = Prop delay+D-FF Delay)...How can it help you cut the delay time to half?...It just blows the issue big,isn't it.So I think the designer must be more specific about using it at the time of designing.we have to consider the additional delay of D-FF introduced while connecting interface A and C(in your eg) and design our interface,right?...ThanksA pipeline register is an ordinary D-flop placed in the middle of combinatorial logic, or in the middle of a long route. It basically divides the propagation delay in half.
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