Re: recover clock from digital data stream have specific fre
firstly, thank EDALIST for your help, but as i see : on Xilinx has some solutions about CDR :
XAPP224 - Data Recovery - but output quite special (see more detail on this App)
Xapp250 - Clock and data Recovery with coded datastream - but appear some other device such as VCO or VCXO (recommend MAXim2605-2609 acording to App Note) and additional circuit quite complex
also as i see - some traditional app using DPLL code quite simple, don't use DCM of FPGA, only use HDL (VHDL, Verilog) to construct
So what is better solution? Can anyone tell me about problem?