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recover clock from digital data stream have specific freq

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ducna

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I have some trouble with problem : from digital data stream have specific frequency (such as E1 - but it is decoded HDB3 - only 1-5V, 0 - 0V) how to recover clock of stream ( the same phase, freq is specific) using FPGA detail on Spartan 3 of Xilinx, some people say to me using DCM (Digital Clock Manager) but DCM can solve this problem? and how
some body known please say to me. Thanks a lot
 

EDALIST

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Re: recover clock from digital data stream have specific fre

CDR is done with a PLL based circuits.
you can use a rocketio transceiver found in virtex2pro o virtex4 for CDR.
check alo xilinx applications.
 

ducna

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Re: recover clock from digital data stream have specific fre

firstly, thank EDALIST for your help, but as i see : on Xilinx has some solutions about CDR :
XAPP224 - Data Recovery - but output quite special (see more detail on this App)
Xapp250 - Clock and data Recovery with coded datastream - but appear some other device such as VCO or VCXO (recommend MAXim2605-2609 acording to App Note) and additional circuit quite complex

also as i see - some traditional app using DPLL code quite simple, don't use DCM of FPGA, only use HDL (VHDL, Verilog) to construct

So what is better solution? Can anyone tell me about problem?
 

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