reconvergence pessimism and derating factor

[sun_ray]

What is clock reconvergence pessimism in a STA timing report? What is Min Data Paths Derating Factor? What is Max Clock Paths Derating Factor? These are usually find in a STA report

 

[yadavvlsi]

Check this:
https://vlsi-expert.blogspot.in/2011/02/clock-reconvergence-pessimism-crp-basic.html
https://www.edaboard.com/threads/189272/

 

[sun_ray]

Can anybody else provide any other materials other than the above two?

 

[vamsi.132013]

Can anybody else provide any other materials other than the above two?

I see some good articles coming up in this website.....You can go through it

https://siliconsaint.blogspot.com

 

[childs]

Some simple explanation base on my memory & understanding:
1. reconvergence pessimism: when running STA with on-chip-variation, says when checking setup time (whether data travels too slow), tool assumes a rather bad scenario for setup: launching clock & data travels slow & capturing clock travels fast. However, if the launch & capture clocks shared some same path, it would be too pessimistic to assume launch clock is slow all along its path & capture clock is fast all along its path (at the common clock path, the same clock edge cannot be slow & fast at same time). This is the meaning of reconvergence pessimism & normally this item will be removed when calculating the path timing report.
2. min/max derating: there are few ways to model slow & fast signals in on-chip-variation mode, derating is one of the way. Max & min derating means to multiply the original timing lib delay values by the derate value. Max derate means the derate for slow condition while min derate for fast condition. You can have different derating factors for clock & data paths.

Hope it helps for quick understanding.