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Receiving incorrect output at receiver FPGA

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ankit rajput

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Hi, I am implementing QPSK transmitter and receiver on two different FPGA (Arty boards) and connecting them through PMod (I/O) pins. I have not implemented any clock recovery at receiver FPGA. So, sometime output is coming correct and sometime gliches are coming in output. let me explain further using waveforms.


Capture_correct.JPG
correct output is coming.


here above shown waveforms are of producing correct data. concat is input to receiver fpga . ce_50_net is clock enable i.e point where we are reading or triggering concat. gateway is output. so here, when ce_50_net signal is triggering input signal between yellow marker and middle of concat signal, i am getting correct output.



Capture_wrong.JPG
wrong output is coming

here above shown waveforms are of producing wrong data. concat is input to receiver fpga . ce_50_net is clock enable i.e point where we are reading or triggering concat. gateway is output. so here, when ce_50_net signal is triggering input signal between middle of concat signal and blue marker, i am getting wrong output.



so some time correct output coming and some time due to chane in triggering position wrong output or output with gliches are coming.

How can i solve this problem?
 

How do you expect that the design can work without some kind of clock synchronization?
 

thanks for reply.

since i have never implemented any clock synchronization , is there any source about implementing it in FPGA?
 

you are generating ce_50_net from a faster clock. in this case, you want to use the two-register synchronizer on the inputs to avoid metastability. after that, implement an edge detector (register + xor). on any edge, the counter generating clk_50_net is reset. that counter also resets if it reaches the normal terminal count. clk_50_net is generated by comparing the counter to something like half of terminal count. This is a simple version of clock recovery.

when the rx clock is slow, the counter will reset a bit before the terminal count happens. if the rx clock is fast, the counter resets and resets a second time with a low count. But these only happen when there are transitions, otherwise it falls back to being a little fast or a little slow. The length of data you can receive where there are no transitions is based on how long it takes the difference in clock frequencies between sender/receiver to accumulate enough phase error to skip/slip a bit.

This is a simple version. there are more advanced methods.
 
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