Reasons behind limitations of unpacked arrays in Systemverilog

[shaiko]

Hello,

Systemverilog unpacked arrays have quite a few limitations compared to packed arrays.
I especially don't understand why they weren't made to support arithmetic operations.
What's the driving motivation behind the limitations ?

 

[dave_59]

When compared to Verilog, unpacked arrays in SystemVerilog have much more functionality. Although Verilog allowed multiple unpacked dimensions, you could only access one element at a time; never the array as a whole. I think this was driven by the RTL synthesis that you cannot operate on memories as a whole in hardware.

SystemVerilog added the ability to pass whole arrays (or slices) through ports and as arguments to tasks and functions. This meant it also had to define array assignments, and comparison operations as well. There's no reason preventing further enhancements, but a few things I can think of are

1. unpacked arrays have stronger types than packed arrays. It's much easier to pad and truncate packed integral values as needed for logical/arithmetic operations
2. People were worried about generating to much hardware from simple expressions and not thinking the current state of RTL synthesis requires you to pipeline or multi-cycle the operations manually.
3. Multi-dimensional array arithmetic has many more kinds of operations and we would have to introduce matrix algebra to become really practical.