[SOLVED] $realtobits function in verilog

[raghavkmr]

module real2bits();

real n;
reg  [63:1]b;

initial begin

n = 15.0 ;
$display("n---->%f",n);
$display("b---->%b",b);
#1

b = $realtobits(n);
$display("b---->%b",b);
#10
$finish;

end

endmodule

output is --->

n---->15.000000
b---->xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
b---->100000000101110000000000000000000000000000000000000000000000000



which is wrong for n=15 ,b should be 1111

why this is happening

 

[andre_luis]

$display("b---->%b",b);

Try replacing the above expression by:

$display("b---->%0b",b);

 

[dave_59]

If you want b to have the value 'b1111, then just do b = n;

$realtobits returns the simulator's internal representation of a real/floating number. It's only purpose in Verilog was that was the only way to pass a real value through module port. You would then use the $bitstoreal function to convert the value back to real without any loss of precision. There is no longer any need for these functions in SystemVerilog because you can pass real types value through ports.

 

[raghavkmr]

Thanks dave ,my problem is solved