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Reading layout file in SoC Encounter

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Abdo18

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The analog design engineer made some modifications on the design layout in Cadence Virtuoso, and he wants me to check timing of the digital core in the modified design using SoC encounter. What file can he generate that I can read?
 

a DEF file with the new routing should work. for the cell placement, I am not sure there is a convenient way.
 

ThisIsNotSam said:
a DEF file with the new routing should work. for the cell placement, I am not sure there is a convenient way.
Click to expand...

The DEF file generated by Virtuoso doesn't contain any information about the design. It's between 10 and 20 lines only.
 

ThisIsNotSam said:
a DEF file with the new routing should work. for the cell placement, I am not sure there is a convenient way.
Click to expand...
In which view should the DEF file generated in Virtuoso: layout, schematic or abstract view?
 

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