Reading internal signals through a testbench.

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Hi all,
Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module? This is required to match and assert if the program is working correctly. Please help. Thank you.

Best Regards,
 

edaboard

In Verilog testbench its very simple you can refer to submodule signal as follows..

top.sub_module.sub_sub_module.my_signal

Here . is used to seperate the hirarchy!

In vhdl I think you need to use FLI !!!
 

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