masoud.malekzadeh
Member level 1
port map
Hi, I'm trying to read data from text file and store it into a ROM the add ROM(0) and ROM(1) using Xilinx IP Core Generator
I'm getting this error in port mapping line :Indexed name is not a std_logic_vector
If I declare ROM type std_logic_vector instead of Bit_vector the reading wo'nt work and i get errors such as
read needs 3 component
Line is not declared
Read is not declared ....
I would be thankful if someone help me .........
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;
entity ROM is
port (
clk: in std_logic
);
end ROM;
architecture Behavioral of ROM is
type ram_type is array (9 downto 0 ) of bit_vector(31 downto 0 );
signal ram :ram_type;
signal w:std_logic_vector(31 downto 0);
signal z:std_logic_vector(31 downto 0);
signal f:std_logic_vector(31 downto 0);
component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;
begin
g1: adder port map (a => ram(0),b => ram(1),clk => clk,result => w); ---------ERROR HERE------
process(clk)
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: bit_vector(31 downto 0 ) ;
variable i :integer range 9 downto 0 :=0;
begin
if(clk' event and clk='1') then
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
i:=i+1;
write(out_line,int);
writeline(outfile,out_line );
end if ;
end process;
end Behavioral
Hi, I'm trying to read data from text file and store it into a ROM the add ROM(0) and ROM(1) using Xilinx IP Core Generator
I'm getting this error in port mapping line :Indexed name is not a std_logic_vector
If I declare ROM type std_logic_vector instead of Bit_vector the reading wo'nt work and i get errors such as
read needs 3 component
Line is not declared
Read is not declared ....
I would be thankful if someone help me .........
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;
entity ROM is
port (
clk: in std_logic
);
end ROM;
architecture Behavioral of ROM is
type ram_type is array (9 downto 0 ) of bit_vector(31 downto 0 );
signal ram :ram_type;
signal w:std_logic_vector(31 downto 0);
signal z:std_logic_vector(31 downto 0);
signal f:std_logic_vector(31 downto 0);
component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;
begin
g1: adder port map (a => ram(0),b => ram(1),clk => clk,result => w); ---------ERROR HERE------
process(clk)
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: bit_vector(31 downto 0 ) ;
variable i :integer range 9 downto 0 :=0;
begin
if(clk' event and clk='1') then
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
i:=i+1;
write(out_line,int);
writeline(outfile,out_line );
end if ;
end process;
end Behavioral
Last edited: