reading data from text file

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masoud.malekzadeh

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I want to read data from text file and load it to a ram but i get these errors :

read expects 3 arguments
Type void is not an array type and cannot be indexed

i would be thankful if you help me .

here is my code :

Code: 
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;

entity ICA is

	port (	x_out:out std_logic_vector(31 downto 0);
	w:in std_logic;
	z:in std_logic;
	clk: in std_logic
	);
	
end ICA;

architecture Behavioral of ICA is



   begin 
	  
process(clk)

    FILE infile : TEXT IS IN "in_code.txt";
   
     variable  my_line : line;
     variable int: std_logic_vector(31 downto 0 );
	  type ram_type is array (3 downto 0 ) of std_logic_vector(31 downto 0 );
	  type TEXT is file of std_logic_vector;
variable ram :ram_type;
	begin 
if(clk' event and clk='1') then 

    for i in 3 downto 0 loop 
readline(infile,my_line);
read (my_line,int);

    if (w='1') then  
	    ram(i):=int ;
		  else 
		  
		 x_out<=ram(i);
		 
		 end if ;
end loop ;
end if ;
end process; 
end Behavioral;
 
Last edited by a moderator:

You have several problems here.

First, do not redefine the text file type. It is already declared in textio.
second, to read std_logic_vectors from a text file use the std_logic_textio package.
third : I assume you understand this is just for simulation. You cannot compile it
fourth: any reason you are using VHDL 87 file syntax rather than 93?
 

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Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;



entity ICA is

	port (
--	x_in1: in std_logic_vector(31 downto 0);
--	x_in2: in std_logic_vector(31 downto 0);
--	x_in3: in std_logic_vector(31 downto 0);
--	x_in4: in std_logic_vector(31 downto 0);
--	y_in: in std_logic_vector(31 downto 0);
	
	x_out:out std_logic_vector(31 downto 0);
	w:in std_logic;
	z:in std_logic;
	clk: in std_logic
	);
	
end ICA;

architecture Behavioral of ICA is

   begin 
	  
     process(clk)

        FILE infile : TEXT IS IN "in_code.txt";
        type ram_type is array (3 downto 0 ) of std_logic_vector(31 downto 0 );
        variable  my_line : line;
        variable int: std_logic_vector(31 downto 0 );
	     variable ram :ram_type;
	begin 
    
	 if(clk' event and clk='1') then 

        for i in 3 downto 0 loop 
         readline(infile,my_line);
         read (my_line,int);

            if (w='1') then  
	    
       		 ram(i):=int ;
		       
				 else 
		  
		       x_out<=ram(i);
		 
		     end if ;
        end loop ;
end if ;
end process; 
end Behavioral;


i have the same errors , i fixed the firs and the second one , but i dont know the advantage of the last one .....
 
Last edited by a moderator:

you havent fixed the second one, you have not included the std_logic_textio package.

VHDL 93 allows you to open a file in 3 ways rather than 2 - read mode, write mode and append mode:

file infile : TEXT open READ_MODE is "in_code.txt";

Also, with 87 syntax, you can only open a file when you declare it. 93 allows you to open/close files inside processes/functions etc ie. under your control.
 

when i use std_logic_textio package i get these ones

<std_logic_textio> is not declared
<text> is not declared
<line> is not declared
<readline> is not declared.
<read> is not declared.

and so on ....
 

how are you trying to compile this? you cannot compile this in quartus or ISE. This can only be compiled in a simulator.

As for std_logic_textio, it is a library:

use ieee.std_logic_textio.all;
 

I'm using ISE in simulation mode and i have the used use ieee.std_logic_textio.all; but i have the same problems ....

do you know any better way to read my data ?
 

I think you are smart enough to use the search function in this forum.

The topic reading text from file has been handled a lot of times
 

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