Hi,
I have a video stream:
SAV :- Start of Active video
EAV :- End of Active video
Valid :- Valid video stream indicator
din(7 downto 0) :- Video Stream
Stream_Ready :- From component where stream is going.
I put a block RAM IP (xilinx) as buffer in between as follows:
For a single port RAM, depending on the options used if you are using a read before write RAM the read operation will occur before the write so you won't see any of the data written until you cycle through all address of the RAM. If that is not the behavior you want then use a simple dual port RAM as FvM suggests.