Reading a block RAM Xilinx IP Core

[beginner_EDA]

Hi,
I have a video stream:
SAV :- Start of Active video
EAV :- End of Active video
Valid :- Valid video stream indicator
din(7 downto 0) :- Video Stream
Stream_Ready :- From component where stream is going.
I put a block RAM IP (xilinx) as buffer in between as follows:

---

Code VHDL - [expand]
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process (inter_clk,sys_rst)
begin
if sys_rst = '1' then
dina <= (others=>'0'); 
elsif rising_edge(inter_clk) then
if Stream_Ready= '1' and Valid = '1' then
Valid1 <= Valid;
SAV1 <= SAV;
EAV1 <= EAV;
dina <= din(7 downto 0); 
addra <= addra + 1;
else
Valid1 <= '0';
SAV <= '0';
EAV <= '0';
dina <= (others=>'0'); 
addra <= (others=>'0'); 
end if;
end if;
end process;
 
stream_ram_inst : stream_ram
PORT MAP (
clka => inter_clk,
ena => '1',
wea => Valid1,
addra => addra,
dina => dina,
douta => douta
);

---

and observe douta but nothing is coming out. Although all input I observe is correct.
How to read from RAM? Am i doing some mistakes here?

 

[dpaul]

stream_ram_inst : stream_ram
PORT MAP (
clka => inter_clk,
ena => '1',
wea => Valid1,
addra => addra,
dina => dina,
douta => douta
);

Whatever you have shown is logic to write-in data. I don't see any logic to read-out the data being written!

I also doubt the correctness of your instantiation of your 'stream_ram'. Recheck this.

 

[FvM]

The RAM will continuously read the content selected by addra and show it at douta port. You should be able to see it.

To read RAM content independent of write action, you'll probably want a dual port RAM with separate read address.

 

[ads-ee]

For a single port RAM, depending on the options used if you are using a read before write RAM the read operation will occur before the write so you won't see any of the data written until you cycle through all address of the RAM. If that is not the behavior you want then use a simple dual port RAM as FvM suggests.