hi...
right now, i am doing size modulation.
my work plan is as follows:
1) size modulation
-> cell ratio (pull down to access transistor)
-> pull up ratio (pull up to access transistor)
2) voltage modulation
-> bit line voltage
-> word line voltage
-> data retention voltage
but, i came to know that this all are inter dependent.
like.... if i will change pull up transistor width then my CR can be changed.
so, i confused. there are so many combination of Wp, Wa and Wn.
so how can i proceed further ?
what should be my proper work flow ?
thanks a lot for reply....
It is a real multi-dimensional optimization problem, where a set of spec (write time, power, stability, area, ...) depend on a set of design parameters (cell ratio, bit line voltage, ...). There are additional parameters like temperature and process variation that you cannot influence, but you have to consider during optimization because they have a strong effect on the performance.
Such problems are best solved by numerical circuit optimization software. If you do it manually without such software, then you have only a choice between two bad approaches:
a) equation-based: quite tedious and error-prone to develop, only rough approximations, not good for multi-corner
b) one-by-one: tune one spec after the other by its most sensitive parameter. Works for simple analog circuits that are constructed with this method in mind, but not well for your problem with trade-offs and no simple 1:1 mapping between parameter and spec.
Disclaimer: my company (
www.muneda.com) sells circuit optimization software, some use it for bit cell optimization, you can check the website. If you are more scientifically interested in developing the algorithm for yourself, you could also try with Matlab.