Read-During-Write in RAM in Digital Circuits

[matrixofdynamism]

One important case to consider when designing memory circuits (RAM) using VHDL or otherwise is the read-during-write behaviour. It could be new value, old value or undefined and special logic may be required to prevent undefined behvaiour. Could you give me an example of scenario where we would want the old valur and an example of where we would want a new value? I am not sure where people would actually do a read during write of the same location, it does not seem to be a good idea.

 

[K-J]

One important case to consider when designing memory circuits (RAM) using VHDL or otherwise is the read-during-write behaviour. It could be new value, old value or undefined and special logic may be required to prevent undefined behvaiour. Could you give me an example of scenario where we would want the old valur and an example of where we would want a new value? I am not sure where people would actually do a read during write of the same location, it does not seem to be a good idea.

If specific 'read during write behavior' is important, then there is a fundamental flaw in the system design that is allowing this to be an 'important behavior' in the first place.

A common example where one would have a 'read during write' would be a simple FIFO that happens to be empty. On the output side of the fifo, the data is being sourced by a memory that is addressed by a read pointer that is pointing at address 0 and is being read on every clock cycle. On the clock cycle when that fifo first gets written, the write pointer is writing to address 0 of that memory, therefore you have a 'read during write'. Since a fifo is generally considered to be a 'good idea' and a fifo does perform 'read during write' at least sometimes, your statement that it is not a good idea to read during write is not correct.

Even if you consider non-synchronous types of memory that aren't really applicable to FPGA types of designs, the fifo again provides a good example. The fifo presents 'empty' and 'full' flags that are used to control adding data to and removing data from the fifo. A 'read during write' to a non-synchronous memory that perhaps produces glitches on the memory output data during that time would not be relevant because the 'empty' flag would not yet be set. Using the flags to control the fifo (and not the data) would be an example of how one would avoid a 'fundamental design flaw in the system design' as I mentioned in the first paragraph.

Bottom line is that the 'read during write' behavior of a memory should not be allowed to become a factor in any good design. It shouldn't matter.

Kevin Jennings

 

[KlausST]

Hi,

it does not seem to be a good idea.

You are talking about dual port ram.
I´m with you. It is no good idea. Without synchronization of both partners you can never be sure what data you read.

I recommend to split the ram into different blocks.
* one where data is wirtten
* one where data is being read.
* and at least one spare to be able to switch the blocks
and a handshaking communication.

There should be a lot of information around how to set up a mulitport memory system.

Klaus