reading image file in vhdl
I guess you require the testbench to act as a behavioral model of your design and downsample the image, so that you can compare it with design output. If this is your intention, you can use any other script like perl, shell script or C/C++ or MATLAB to downsample the image. Store the output in normal text format. Use your testbench only to read the image, feed the design inputs and capture the output. Then using another script you can compare the design output file with actual downsampled output from the script.