how to write test benches such that it will work like a feedback machine?
I need the output of the VHDL programme as the next input in the testbench. if there is any link where I can read about it then that will be of great help.
The 'Source' shown above need not not be a separate module. It can be a part of your TB.
There is nothing special here.
Just connect the top level ports of your DUT to the testbench and drive your ports as they should be. As per feedback from the DUT, a checker logic can be placed in your testbench that will say whether the received data is correct or not.
Implementation will vary wildly based on the DUT, but the general idea is that the TB waits for some event from the DUT before deciding how to generate the next input data (or sequence of input data).
now I have a different issue. I wrote a VHDL code for synchronous demodulation. I use vivado 2016.4. it works perfectly with a testbench in the software. but when I burnt the code into the FPGA board (Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)) it doesnt work. any suggestions?
I used a software called terra term to read the output from the board. it is serial communication. nothing is wrong with the board. I tested the board with a different code and it worked. since it works fine in the simulation i couldnt find the error in my code.
Well first of all this is a different issue and technically you should have created a new thread for this.
Now as to what could go wrong....many things!
1. Did your design implementation process pass 'timing'? Have you properly constrained your design?
2. Was the FPGA pin-mapping done properly?
3. An ILA core can be inserted anywhere into your design and the internals signals can be 'probed' to find out what is actually happening inside.
4.
I used a software called terra term to read the output from the board.
thank you for responding. after the simulation, I implemented the design and ran a post-implementation timing simulation. it said all my timing constraints are met. and the tera term baud rate and fpga pin maping are checked. they are propper.
even I have no idea how to add more details about my issue!
Then as per my post #7, you should go for further debugging using <3>.
If you don't know about ILA core and how to use them, read the related Xilinx documentation first.
Again, this problem of yours should be a separate post and should be posted in the FPGA section. Moderators please take a note of this!
I 'll post this as a separate thread. thank you for mentioning ILA. I have read more about it from the xilinx docs. now I am trying to add ila IP core to my design