Re: delay code in vhdl
thank you sivamani and FvM... I wrote the code like (only architecture part)
architecture Behavioral of ctr is
begin
process(clk)
variable cnt:integer:=0;
begin
loop
--wait until clk='1';
cnt:=(cnt+1) mod 65535;
if(cnt=65535)then
c<=cnt;
end if;
end loop;
end process;
end Behavioral;
It is showing the error like
ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.
how to resolve this..
Why cant you write code in this way?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LED is
port
(
D : out std_logic_vector (3 downto 0);
clk_50MHz : in std_logic;
reset_n : in std_logic
);
end entity;
Architecture behaveior of LED is
signal count :std_logic_vector(19 downto 0);
signal Data :std_logic_vector (3 downto 0);
Signal rst_low :std_logic <= "0";
begin
Process(clk_50MHz)
if rising_edge(clk_50MHz) then
if (reset_n = rst_low) then
count <= (others => '0');
data <= "0000";
else
count <= count + '1';
if(count = 0) then
data <= data(0) & data(3 downto 1);
end if;
end if;
end if;
end Process;
D <= data;
end behaveior;
---------- Post added at 05:31 ---------- Previous post was at 05:30 ----------
Why cant you write code in this way?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LED is
port
(
D : out std_logic_vector (3 downto 0);
clk_50MHz : in std_logic;
reset_n : in std_logic
);
end entity;
Architecture behaveior of LED is
signal count :std_logic_vector(19 downto 0);
signal Data :std_logic_vector (3 downto 0);
Signal rst_low :std_logic <= "0";
begin
Process(clk_50MHz)
if rising_edge(clk_50MHz) then
if (reset_n = rst_low) then
count <= (others => '0');
data <= "0000";
else
count <= count + '1';
if(count = 0) then
data <= data(0) & data(3 downto 1);
end if;
end if;
end if;
end Process;
D <= data;
end behaveior;
this code for roling leds with around 300ms time