RDRAM Controller and FPGA interfaces

[mami_hacky]

RDRAM Controller

Any body has developed any controller design for RDRAM devices? I have never seen any app note or data from any of FPGA vendors for interfacing between FPGA and these high performance DRAMs. Any body can describe the reason? May be, they need a high clock frequency to work properly.

For ASIC design of these controllers, any body can help me about the points and tricks we should know, while developing the design?

 

[edaguy69]

No one design controller for RDRAM by FPGA because of two factors: cost and performance. A FPGA chip cost at least $100.00 and max speed is around 400MHZ. while RDRAM working speed is at least 800MHZ. Rambus have an army of PhDs working on these design. Why are you interested in this field?

 

[mami_hacky]

OK! I think RDRAM may be a good choice for doing random accesses to big memories. The problem which I solved ( for my design ) using a 200 MHZ DDR SDRAM.
Am I wrong? How are the latencies in a RDRAM device?

Finally there is one additional point, many of big designs are implemented on a FPGA before porting to ASIC. So, I think I should be able to test the performance of my RDRAM controller, before making the final chip.

 

[igorsat]

One of the reasons is probably high royalties which FGPA companies are not willing to pay to RAMBUS. Based on the RDRAM chip documentation from Samsung I can see that RDRAM controller is not so simple to build as the DDR. Full implementation would take quite a lot of slices. From the technological point of view I see the problems elsewhere. RDRAM interface is some sort of LVDS interface. Last year I designed several LVDS interfaces, which are working at 380MHz (Virtex II XC2V1000-4) max and it was extremely difficult to get them working at that freq. RDRAM interface is working at even higher frequencies and I suppose this is big problem for FPGAs.
I’m also looking for any signs of RDRAM controller in FPGAs especially for Xilinx, but so far no luck. I’m faced with the design, where I will have to connect at least 16-32GB and probably even more of RAM to FGPA device. Currently I’m using dual channel DDR working at 225MHz and on each channel I was able to connect three custom made DDR modules. Each module is 1GB in size. That totals 6GB, which is far from 16-32GB. I’m thinking of 4 channel interface but this would be too expensive and very hard to implement, because of the signal integrity issues and of course I don’t want to use all FPGA pins for DDR interface. RDRAM is a point to point interface and I would be able to connect even 32 modules in serial on one channel, but as you already pointed out, there are no application notes on the net. It seems that all designers are NDAed. It also seems there aren’t any “RDRAM” controller chips available on the market. So, if anyone finds valuable data how to build RDRAM controller in FPGA, I would be extremely thankful.

If you connect several RDRAM modules in serial the latency should increase, because the signals would have to travel through all devices (if the target write or read address is in the last RDRAM module). But, because the bus is pipelined and transaction oriented this latency could be compensated after the initial delay. If I’m wrong please correct me.

igorsat