nasdrasil
Newbie
Hi! I'm a starter using FPGA's and was hoping somebody here could point me in the right direction...
To code my iceFUN ice40 HX8K I use icestudio.
I am pulling a 5 bit wide signal into my iceFUN board. This signal contains pixel data from a retro computer. The machine also makes sync with this signal but is missing serration pulses in the vertical interval which makes it unusable on most tv's.
I am using a modeled piece of ROM that creates 3-3-3 bit RGB output. I can verify the output of this ROM with the original signals created inside the machine and they are a perfect match, datawise, timewise and phasewise, which tells me that my modeled ROM is at least functioning the way it should.
Besides the pixel data I want the fpga to create a new, proper sync signal, so I created a seperate module with two counters setup to create the appropriate sync pulses. I use the machines 4mHz clock for this. I can verify my created sync against the machines internally created sync signal. My generated sync on it's own is spot on, but...
Every time on power-up there is a random phase mismatch between the pixel data from the ROM and the sync signal my counters create. It's as if the counters start counting on a random number, but I do set the counter registers to 0. Sometimes sync will be ahead, sometimes behind. ROM and sync generation is both on the machines 4 mHz clock that I pull in.
I am very interested in what could be causing the phase difference between the pixel data and sync signal. The randomness to it is something that puzzles me. I had somebody giving me the clue that my counters had no initial value, so I gave them both an initial value of 0, which did not help my problem.
Not looking for a ready made solution since I consider this a learning project, but it would be great of somebody could point me in the right direction
To code my iceFUN ice40 HX8K I use icestudio.
I am pulling a 5 bit wide signal into my iceFUN board. This signal contains pixel data from a retro computer. The machine also makes sync with this signal but is missing serration pulses in the vertical interval which makes it unusable on most tv's.
I am using a modeled piece of ROM that creates 3-3-3 bit RGB output. I can verify the output of this ROM with the original signals created inside the machine and they are a perfect match, datawise, timewise and phasewise, which tells me that my modeled ROM is at least functioning the way it should.
Besides the pixel data I want the fpga to create a new, proper sync signal, so I created a seperate module with two counters setup to create the appropriate sync pulses. I use the machines 4mHz clock for this. I can verify my created sync against the machines internally created sync signal. My generated sync on it's own is spot on, but...
Every time on power-up there is a random phase mismatch between the pixel data from the ROM and the sync signal my counters create. It's as if the counters start counting on a random number, but I do set the counter registers to 0. Sometimes sync will be ahead, sometimes behind. ROM and sync generation is both on the machines 4 mHz clock that I pull in.
I am very interested in what could be causing the phase difference between the pixel data and sync signal. The randomness to it is something that puzzles me. I had somebody giving me the clue that my counters had no initial value, so I gave them both an initial value of 0, which did not help my problem.
Not looking for a ready made solution since I consider this a learning project, but it would be great of somebody could point me in the right direction