I am currently involve in asic design for designing a FFT radix-2 and radix-4 butterfly structure. I have done both design using verilog code. Eventually, i need to do some modification (improvement) on the design as a contribution to my postgraduate studies. Can anyone suggest to me any modification that can be done to the radix-4 fft, so that it can have better performance . Thanks in advance.
o.k
u have a parallel implementation.
u have a lot of mul's and adders right.
why not serialize this??
this would be a good one if u can serialize and wat
type of multipliers and adders have u used.wat
speed have u obtained after synthesis.
Thanks for the reply. My speed for this design is 50MHz. I have used behavioral verilog to do the coding. I am a bit blur on how to implement it in serial. Hope u can give me some guideline on this. Thanks in advance.