alphus
Newbie level 6
Hello.
I'm trying to synthesize the SPI slave in RC Compiler. After synthesis occurs race conditions between SPI_CLK and system clock (clk):
How to avoid the race conditions in this case?
I'm trying to synthesize the SPI slave in RC Compiler. After synthesis occurs race conditions between SPI_CLK and system clock (clk):
Code:
always @(posedge clk)
spi_clk_r <= spi_clk;
How to avoid the race conditions in this case?
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