what is race condition in verilog
Hi Viewers
can anyone explain me in a brief manner for the below qns:
1. what is meant by RACE CONDITION??
Race condition occurs when a latch changes its state from an invalid state to a known state.. For example, if you consider an SR latch, if S and R values change from 1 1 (that results in invalid state) to 0 0 simultaneously, then as latch is level-trigerred and the transistion of the inputs is NOT abrupt, the outputs undergo a series of change in their states which remain unknown to the user till the clock goes negative. This condition is called race condition.
what are the demerits of RACE CONDITION.
the demrits,as explained above , is that you wont know the state of the latch till the colcok goes negative, as the outputs are constantly changing (due to level trigerring)
2. what are differences bet' BLOCKING nd NON-BLOCKING statement?
plz explain with an eg for both statements
Blocking statements are those where the execution of the next statement is BLOCKED till the execution of the current statement is finished.That is the blocking statements are executed sequentially.
However, there is NO delay in executing a set of blocking statements
Non-blocking statements are those wherein all the statements are executed PARALLELY, ie the next statement doent wait for the current statement to be exectued.
Ex.
Blocking Non-Blocking
b = a; b <= a;
c = b ; c <= b;
in the above example, for blocking statements, the value of c is updated to the value of a at the end of execution.
but for non blocking statements , the second statement doesnt wait for the updation of b in the first statement and hence assigns whatever value "b" was holding before the first statement was executed. that is it looks as though both the statements got exectued parallely.
Blocking statements are used while designing combinational logic and nonblocking statements are used for desiging sequential logic.
To others :
Please correct me, if am wrong anywhere