What is a macro ?
A macro is a literal name used in a program that is substituted by some value before the program is compiled. Macros are useful as an alias without using program resources. They are not variables, so you can not assign a value to a macro from within a program. Almost all modern languages, including Verilog, support macro definition.
Macros in Verilog
Macros in Verilog are specified by using `define compiler directive. Here is an example:
`define MY_DELAY 2
...
r1 = #`MY_DELAY 1'b1;