This is one of the issues with VHDL -- it is fairly strongly typed. An integer, for VHDL's purposes, is much different than std_logic_vector, unsigned, or signed. You need to convert the unsigned to an actual integer (to_integer()). Some packages have a std_logic_vector to integer (assuming unsigned) conversion function.
perhaps if you wanted to concatenate or perform logic operations on the bus, or ever planned to make a RAM that had that ability. Or if you wanted to do addition without having to add a modulo operator. I'm not really a fan of VHDL's integer type.
Well in that case yes, use an unsigned type. But if you only need to add 1 to it and index into and array, integer is perfect (it reads best and is most logical).