Quick conversion question

[munchies]

I am having a little trouble when compiling. I am getting the following error:

"Type conversion (to ieee.numeric_std.unsigned) conflicts with expected type std.standard.integer"

From the following

TYPE Mem IS ARRAY ( AddressSize DOWNTO 0) of std_logic_vector (7 DOWNTO 0);
SIGNAL Memory : Mem;
Memory(UNSIGNED(Addr)) <= DataIn;

There is other code but I've left it out, as I think this is the only relevant code.

Is it possible to convert to integer type using only "ieee.numeric_std.ALL"

I would of thought that unsigned could of been considered the same as integer?

 

[permute]

This is one of the issues with VHDL -- it is fairly strongly typed. An integer, for VHDL's purposes, is much different than std_logic_vector, unsigned, or signed. You need to convert the unsigned to an actual integer (to_integer()). Some packages have a std_logic_vector to integer (assuming unsigned) conversion function.

 

[TrickyDicky]

you wil need to convert it:

memory( to_integer(unsigned(addr) ) ) <= DataIn;

Instead of having to do this conversion, why not have Addr as an integer in the first place?

 

[permute]

perhaps if you wanted to concatenate or perform logic operations on the bus, or ever planned to make a RAM that had that ability. Or if you wanted to do addition without having to add a modulo operator. I'm not really a fan of VHDL's integer type.

 

[TrickyDicky]

Well in that case yes, use an unsigned type. But if you only need to add 1 to it and index into and array, integer is perfect (it reads best and is most logical).