Hi All,
I am just new to DFT(Design For Testability).
What are Post-DRC violations?
I have basic idea about Pre-DRC violations like,
Uncontrollable clock input to flip-flop(D1),
Clock feeding data input violations(D2),
D3,D10,etc.
So likewise,which are Post-DRC violations?
Also, I am little bit confused between SE(Scan enable) and TM(Test mode) in DFT.
Can anyone tell me what exactly its difference is?
Can someone please tell me where to use Scan enable(SE) and where to use Test mode(TM)?
I have gone through synopsys use guide of DFT compiler , which says there are 2 Scan insertion methodologies :
1. Bottom-up(building scan chain in each module - combining all at top level)
2. Top-down(From top level building scan chain)
I am not able to understand that where we need which approach?
Can anybody give me any example that where i need to use which approach?
Thank you.
Regards.
Shalin