Questions Concerning Gerneral Methodologies of DFT and Synopsys DFT Compiler

[shalin mandiwala]

As far as i know DRC is some set of rules which must need to follow before scan insertion.
Why we need DRC(Design Rule Checking) in ASIC Design Flow?
While doing DFT which major DRC that must need to be checked?
Is there any general flow to solve any DRC?


Help.
Thank you.

 

[wtr]

I'm assuming DFT means design for test?

What type of DRC errors are you getting?

I tend to ignore ones about incomplete tristate buffers if my DFT is just outputting internal signals. I pay more attention to clock crossing.

It's more like a set of guidelines.

Wes

 

[shalin mandiwala]

Hi All,

I am just new to DFT(Design For Testability).
What are Post-DRC violations?
I have basic idea about Pre-DRC violations like,
Uncontrollable clock input to flip-flop(D1),
Clock feeding data input violations(D2),
D3,D10,etc.

So likewise,which are Post-DRC violations?

Also, I am little bit confused between SE(Scan enable) and TM(Test mode) in DFT.
Can anyone tell me what exactly its difference is?
Can someone please tell me where to use Scan enable(SE) and where to use Test mode(TM)?

I have gone through synopsys use guide of DFT compiler , which says there are 2 Scan insertion methodologies :

1. Bottom-up(building scan chain in each module - combining all at top level)
2. Top-down(From top level building scan chain)

I am not able to understand that where we need which approach?
Can anybody give me any example that where i need to use which approach?


Thank you.
Regards.
Shalin