vhdl ams operators
About your first question : Why VHDL-AMS is faster in comparision with SPICE because VHDL-AMS is a behavioral (top-down design) and SPICE is a netlist (Bottom-Up design). So the signal propagation in SPICE case will be more than in AMS case.
Second question : It's difficult to compare the performance of those equivalent AMS designing tools. Its depends on user familiar only. My friend always find comfortable with CADENCE but i only enjoy SYNOPSYS and Dolphin Smash.
Thirdly : In which industry AMS is used ? Obviously ASIC design. But remember that the simpler the programing language is, the harder it can be realized. We can come to it thru one popular example : A very simple operator * (multiply by a constant) may indicate the amplification process. But to realize it, our link and target ibrary must contains a generic amplifier( or at least few tenth amplifier each with different gain ). Hence by expanding our interest to AMS, we need a very strong and well-updated library designing team. It's the barrier to AMS.
Question no 4 : Which companies prefer AMS ? Plz refer to Google.com .... From my poor knowledge at this moment HSpice still their interest and it will remain for at least few tenth years more ....
Question no 5 : Career prospect for one who are well with AMS .... From my case i can say that it should be unemployed ....
( relax i'm just joking ) ... Its depends on you ...
Question no 6 : Conceptualy there is no different between VHDL-AMS and Verilog-AMS except those operators in Verilog are all most symbolized but VHDL are not.... They are equivalent. If you are new to AMS, it'd better to go for Verilog-AMS in stead of VHDL-AMS.... Verilog is more popular in industry.