hoangnc
Newbie level 4

Hi all,
I'm designing a board which has an FPGA XC3s1500 interfacing with QDR SRAM memories. It works at 100 MHz (effectively 200 MHz because the QDR memory uses both rising and falling edge - DDR). I read some documents about designing high speed PCB but there's something I'm still not clear. Could you help me?
- I wonder whether using series or pull-up termination. I prefer the series termination method because it reduce ground bounce and also because I cannot reduce stub length in the other one (max stub length using pull-up registers is about 1 cm, max routed trace length about 4 cm). Can you give me advice?
- Can I route ouput-only LVCMOS pin to input-only HSTL pin (both work at 1.5 V). I asked this because LVCMOS in XC3S1500 has bult-in series termination while HSTL not.
- I read in on a document that we don't need to place decoupling capacitors just under power pins, instead we can place 0.001uF 1.2 inches away the IC. It's right? Can I place all decoupling around the periphery of the IC?
- Which takes higher priority, having each GND/power pin one via connecting to plane or placing decoupling caps near GND/power pin?
Thanks,
Hoang
I'm designing a board which has an FPGA XC3s1500 interfacing with QDR SRAM memories. It works at 100 MHz (effectively 200 MHz because the QDR memory uses both rising and falling edge - DDR). I read some documents about designing high speed PCB but there's something I'm still not clear. Could you help me?
- I wonder whether using series or pull-up termination. I prefer the series termination method because it reduce ground bounce and also because I cannot reduce stub length in the other one (max stub length using pull-up registers is about 1 cm, max routed trace length about 4 cm). Can you give me advice?
- Can I route ouput-only LVCMOS pin to input-only HSTL pin (both work at 1.5 V). I asked this because LVCMOS in XC3S1500 has bult-in series termination while HSTL not.
- I read in on a document that we don't need to place decoupling capacitors just under power pins, instead we can place 0.001uF 1.2 inches away the IC. It's right? Can I place all decoupling around the periphery of the IC?
- Which takes higher priority, having each GND/power pin one via connecting to plane or placing decoupling caps near GND/power pin?
Thanks,
Hoang