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Questions about termination and PCB layout

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Newbie level 4
May 10, 2004
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Hi all,

I'm designing a board which has an FPGA XC3s1500 interfacing with QDR SRAM memories. It works at 100 MHz (effectively 200 MHz because the QDR memory uses both rising and falling edge - DDR). I read some documents about designing high speed PCB but there's something I'm still not clear. Could you help me?

- I wonder whether using series or pull-up termination. I prefer the series termination method because it reduce ground bounce and also because I cannot reduce stub length in the other one (max stub length using pull-up registers is about 1 cm, max routed trace length about 4 cm). Can you give me advice?

- Can I route ouput-only LVCMOS pin to input-only HSTL pin (both work at 1.5 V). I asked this because LVCMOS in XC3S1500 has bult-in series termination while HSTL not.

- I read in on a document that we don't need to place decoupling capacitors just under power pins, instead we can place 0.001uF 1.2 inches away the IC. It's right? Can I place all decoupling around the periphery of the IC?

- Which takes higher priority, having each GND/power pin one via connecting to plane or placing decoupling caps near GND/power pin?



First, A serial resistor should be place close of the driver.
a pull down should be place close of receiver.
It is depend of FPGA but a serial resistor or termination
is not necessary if Xilinx have FPGA with teminal pins.

I expect that is a 50 ohm trace. Take care to have a 50 ohm.

Decoupling capacitor must be place as close as possible of
power pins. 1.2inchs are too far.

Good luck


As steph told the priority goes to serial termination which must be placed to the source and the parallel termination should be closer to the load.

"having each GND/power pin one via connecting to plane or placing decoupling caps near GND/power pin?"

Having each GND/Pwr via direct to the plane wont solve your purpose.

Decaps must be placed very close to the ic's power pins.

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