verilog concurrent or sequential
What is the function of sensitivity list?
A transition on any one of multiple signals or events can trigger the execution of a statement or block of statements is known as sensitivity list. The signals which are triggered would go into the sensitivity list. The keyword OR is used to specify multiple triggers. Sensitivity list can also be specified using the “,” (comma) operator instead of the OR operator.
Is Verilog (or that matter any HDL) is a concurrent or sequential language?
The difference between C and HDL is HDL are concurrent, whereas C is sequential.
so verilog & VHDL r concurrent (=>)