Questions about sensitivity list in Verilog and what type of language is Verilog

[phoenix_pavan]

Is Verilog (or that matter any HDL) is a concurrent or sequential language?

What is the function of sensitivity list?

Why would a testbench not have pins (port) on it?

When declaring a flip flop, why would not you declare its output value in the port statement?

 

[research_vlsi]

verilog concurrent or sequential

What is the function of sensitivity list?
A transition on any one of multiple signals or events can trigger the execution of a statement or block of statements is known as sensitivity list. The signals which are triggered would go into the sensitivity list. The keyword OR is used to specify multiple triggers. Sensitivity list can also be specified using the “,” (comma) operator instead of the OR operator.

Is Verilog (or that matter any HDL) is a concurrent or sequential language?

The difference between C and HDL is HDL are concurrent, whereas C is sequential.
so verilog & VHDL r concurrent (=>)

 

[Tan]

Re: verilog questions

The difference between C and HDL is HDL are concurrent, whereas C is sequential.
so verilog & VHDL r concurrent (=>)

How come verilog and VHDL are concurrent languages??can you explain in detail...
i think verilog and vhdl have both concurrent and sequential execution in it..

Added after 35 seconds:

The difference between C and HDL is HDL are concurrent, whereas C is sequential.
so verilog & VHDL r concurrent (=>)

How come verilog and VHDL are concurrent languages??can you explain in detail...
i think verilog and vhdl have both concurrent and sequential execution in it..

 

[research_vlsi]

Re: verilog questions

yes i agree both has sequential and concurrent executions..

In verilog blocking statements r sequential, non blocking r concurrent...

 

[shobhitk]

verilog questions

Yes Tan u are right Inside process all the statements are sequential while others are concurrent. In Verilog we have blocking = and non blocking <= assigments .

 

[Tan]

Re: verilog questions

Hi shobhitk,
Please explaine me why blocking is used for sequential and non blocking for concurrent..i am unable to understand...
thank you in advance..

 

[pramodm]

verilog questions

reading of any HDL book will clarify your questions

 

[standardon]

verilog questions

sensitivity list actuare is use for simulator!

 

[ljxpjpjljx]

Re: verilog questions

I think you can ask for a book to answer all question!