lhlbluesky
Banned
i have designed a pipelined adc which has a differential output of -0.6~0.6V for smic 0.18um process,but i have some questions:
first,the capacitance of the capacitor is multiple of 606.875ff(25*25um^2),how to change the value of capacitor for arbitrary value uch as 500ff 400ff or so?
second,i want to test my adc for some dc input value(some points only,i will use sine test later),but i find that when the input value is near the threthold of comparator,in my case,+-150mv,+-300mv and 0 for the last stage,the output will change,in the first three or four cycle,the output is a code,and for later cycles,it will be another code;or for the two and three cycle ,the output is a code,and for other cycles,it will be another code;in a word ,the output code can't maintain a code permanently;why?later,i find that the differential output of the first stage(for some cycle,such as the two and three cycle)is not 0(for 0 differential input),and has a value of 4~6mv or so,and multiplied by 2 for 7 times,as a result,the output code is wrong for some certain cycles;what's the reason,why?(i use a voltage referenve circuit to generate the signal vdac+ vdac- and vcm,and for this case,the three signal can't be stable for the relative cycles,that is,the three signal can't settle stably in the cycle which has wrong output code as the above mentioned).
third,my adc is 10 bit resolution,if i have a 10 bit output d10~d1,how to convert it into matlab for parameter measurement(SNR SINAD ENOB INL DNL and so on)?and how to measure the performance(parameter) of my adc in matlab?
thanks all for reply.waiting for your answer.
first,the capacitance of the capacitor is multiple of 606.875ff(25*25um^2),how to change the value of capacitor for arbitrary value uch as 500ff 400ff or so?
second,i want to test my adc for some dc input value(some points only,i will use sine test later),but i find that when the input value is near the threthold of comparator,in my case,+-150mv,+-300mv and 0 for the last stage,the output will change,in the first three or four cycle,the output is a code,and for later cycles,it will be another code;or for the two and three cycle ,the output is a code,and for other cycles,it will be another code;in a word ,the output code can't maintain a code permanently;why?later,i find that the differential output of the first stage(for some cycle,such as the two and three cycle)is not 0(for 0 differential input),and has a value of 4~6mv or so,and multiplied by 2 for 7 times,as a result,the output code is wrong for some certain cycles;what's the reason,why?(i use a voltage referenve circuit to generate the signal vdac+ vdac- and vcm,and for this case,the three signal can't be stable for the relative cycles,that is,the three signal can't settle stably in the cycle which has wrong output code as the above mentioned).
third,my adc is 10 bit resolution,if i have a 10 bit output d10~d1,how to convert it into matlab for parameter measurement(SNR SINAD ENOB INL DNL and so on)?and how to measure the performance(parameter) of my adc in matlab?
thanks all for reply.waiting for your answer.