questions about pipelined adc;

[lhlbluesky]

i have designed a pipelined adc which has a differential output of -0.6~0.6V for smic 0.18um process,but i have some questions:

first,the capacitance of the capacitor is multiple of 606.875ff(25*25um^2),how to change the value of capacitor for arbitrary value uch as 500ff 400ff or so?

second,i want to test my adc for some dc input value(some points only,i will use sine test later),but i find that when the input value is near the threthold of comparator,in my case,+-150mv,+-300mv and 0 for the last stage,the output will change,in the first three or four cycle,the output is a code,and for later cycles,it will be another code;or for the two and three cycle ,the output is a code,and for other cycles,it will be another code;in a word ,the output code can't maintain a code permanently;why?later,i find that the differential output of the first stage(for some cycle,such as the two and three cycle)is not 0(for 0 differential input),and has a value of 4~6mv or so,and multiplied by 2 for 7 times,as a result,the output code is wrong for some certain cycles;what's the reason,why?(i use a voltage referenve circuit to generate the signal vdac+ vdac- and vcm,and for this case,the three signal can't be stable for the relative cycles,that is,the three signal can't settle stably in the cycle which has wrong output code as the above mentioned).

third,my adc is 10 bit resolution,if i have a 10 bit output d10~d1,how to convert it into matlab for parameter measurement(SNR SINAD ENOB INL DNL and so on)?and how to measure the performance(parameter) of my adc in matlab?

thanks all for reply.waiting for your answer.

 

[lhlbluesky]

anyone can help me, pls?

 

[gunturikishore]

You need to be more specific about your problem. The information you gave is a bit confusing.

I don't know why you cannot decrease the capacitance in your first question. You can have smaller unit caps and combine them according to your design requirement.

From your second question what I understand is your amplifier might be not reaching its final value. I designed a pipeline ADC with 8-bit resolution and the first stage never shows an offset more than 0.5 mV and it is almost constant throughout its full scale operation. First check that all the waveforms and the transients are reaching their final value.

How many bit resolution stages you designed at each stage?? For 1.5 bit resolution stages you need only two comparators +-150 mV for your design. Where does those +-300mV comparators come from??

 

[lhlbluesky]

in spectre, the capacitance of the capacitor can't change, it's gray;that is , the only parameter which can change is the multiplier of capacitor; is it the problem of techfile or any other reason?

second,for 10 bit 1.5bit per stage,the last stage has no RSD, so three comps are needed,and three thresholds are needed ,that is, -300mv 300mv 0 .

 

[amriths04]

i guess the capacitor problem is surely due to your techfile. just try changing the length or the width of the caps to change its values.

regarding your second problem it is quite confusing. do you mean only at those particular values your MDACs show this behaviour, or everytime? does the code change only by an LSB or are you able to find any pattern in that?

use an ideal dac to convert the 10 bits into values between 0 and 1023 for an input sinusoid. from there you can calculate its sndr, enob, sfdr. for dnl, input a ramp and find the percentage step size change from the ideal expected one.

in spectre, the capacitance of the capacitor can't change, it's gray;that is , the only parameter which can change is the multiplier of capacitor; is it the problem of techfile or any other reason?

second,for 10 bit 1.5bit per stage,the last stage has no RSD, so three comps are needed,and three thresholds are needed ,that is, -300mv 300mv 0 .