qilongliu
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Hi everyone,
Recently I am using TSMC .18 mixed-signal technology to do some design. I am about to use a deep nwell to put all my digital circuit into it to get a good noise isolation. However when I run LVS I found all the NMOS of those digital standard cells are recognized as the dnw NMOS. I know I can use dnw NMOS in the analog part, but for the digital part it might be hard to modify the NMOS type in the schematic in order to pass LVS. So is there any solution to such a problem? I guess there should be but I cannot find it...
PS: I also try to tie the P substrate of such a nmos to the region outside the deep n well to to have a good connectivity. But it doesn't work either...
Thanks in advance!
Qilong
Recently I am using TSMC .18 mixed-signal technology to do some design. I am about to use a deep nwell to put all my digital circuit into it to get a good noise isolation. However when I run LVS I found all the NMOS of those digital standard cells are recognized as the dnw NMOS. I know I can use dnw NMOS in the analog part, but for the digital part it might be hard to modify the NMOS type in the schematic in order to pass LVS. So is there any solution to such a problem? I guess there should be but I cannot find it...
PS: I also try to tie the P substrate of such a nmos to the region outside the deep n well to to have a good connectivity. But it doesn't work either...
Thanks in advance!
Qilong