Questions about cascode

promach · Jun 15, 2018

For these cascode circuits , could anyone explain why it is 2*Vt + Vsat for the last two circuits (c) and (d) ?

I will deal with the output impedance derivation later and will come back to this thread if I face problem during derivation.

All screenshots are extracted from **broken link removed** or View attachment CMOS ACTIVE INDUCTORS springer.pdf

nitishn5 · Jun 15, 2018

From my understanding it should be Vt + 2*Vsat.

M3 Gate (or M2 Source) would be at Vt + Vsat,M3.
For M2 to be in saturation, minimum voltage at drain would be M2,Source + Vsat, giving us the minimum Vdd as Vt + Vsat,M3 + Vsat,M2
Or simply Vt + 2*Vsat.

This is unless we deliberately size M3 small, such that Vsat,M3 = Vt. But why would we do this?

Nitish

promach · Jun 15, 2018

M3 Gate (or M2 Source) would be at Vt + Vsat

if M3 is NMOS, saturation requirement should be Vgs3 < Vth + Vds3 and Vgs3 > Vth

are you saying that I should take the value of Vgs3 since it is larger compared to Vds1 ?

nitishn5 · Jun 17, 2018

The drain of M1 is being set by the amplifier loop (M3, (M4), M2).
That will set it to Vgs,M3 = Vt + Vsat,M3.

M1 cannot do much to set its own Vds as it is in open loop.

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