[Question] What is "scan test"?

[GDF]

In logic ICs we have one pin for scan test, what's the purpose of this?
what is "scan test" ?
thanks,

 

[shiv_emf]

DFT scan check ...
testing for defect in manufacturing of silicon chip !!

 

[Thinkie]

Scan test is the methodology where registers in a design are connected with a long chains. These registers are pre-loaded with specific values shifting serially values using the scan chains. Then we clock once the design and capture the inputs of these registers. These values are shifted out and the results are read and checked againsts expected values.

This is scan test in one paragraph

 

[dft_guy]

If you have a specific 'scan_test' pin, then that is the pin to put the device into scan mode, so that it can run ATPG (Automatic Test Pattern Generation) vectors, for manufacturing test. Many devices use this 'scan_test' signal to disable clock gating and sequentially derived asynchronous resets, which is necessary during scan test.

John
DFT Digest

 

[vinodkumar]

Hi,As testing is an costlier effort,the designs r made in such a way tht they r easily testablefor ICs in which registers r involved registers r replaced with scan register which r made easier for testability,basically the concept is easily testing the IC.one of the procedure is scan test.for more info refer DFT by abromovicci.

 

[eltonjohn]

scan test or JTAG is a serial protocol included in some complex chips to diagnose the port functionality ..all components with Jtag are link together in a daisy chain maner .So is possible to send test patterns and test if the ports work .JTAG is also employed to load FIRMWARE in FLASAH or eeprom in MIcrocontrollers.And to do debug

 

[tdminion]

This is an old post, but...

what are the chip level I/O's associated with scan chains? specifically, how do you control the scan test and shift in/out of the scan chains (from the I/O's)? All the documents that I read only discuss a scan cell connecting to another scan cell. Are scan_in, scan_out, scan_en chip level I/O's? If so, does each scan chain have dedicated chip-level I/O?

 

[jducluzeau]

There are some scan inputs and outputs at the chip level I/Os but there are probably muxed.
It means this I/Os are some different function at normal mode.To use this I/Os as scan_in you need to go to scan mode.
Sometime for small design there are enough I/Os and scan_in can be directly accessed.

Regards
Jerome

 

[ConradATPG]

You need to provide a better description of the chip DFT facilities.

It could be that it uses pins to control the DFT logic or operates through JTAG.

If it uses pins to control the DFT logic there are most like the following pins:

test/functional pin
shift/no shift pin
test clock pin
scan in pin
scan out pin (output pin)

JTAG has the following pins:

TDI (Test Data In)
TDO (Test Data Out)
TCK (Test Clock)
TMS (Test Mode Select)
TRST (Test Reset) optional.

 

[design_oriented]

SCAN tests from a chip testing perspective also talk about coverage meaning how much of the logic can be tested. Depending on the design coverage numbers can be anywhere between 90 - 98% (< 100%). The main advantage of SCAN tests is a lot of logic can be tested very quickly. SCAN tests are generally not checking for speed problems but are looking for stuck at faults (logic 1 or 0) in the design.