pll clean up loop
You did not say what type of phase error you are trying to eliminate (error from a phase step perturbation, phase ramp, doppler frequency shift, etc). Assuming the simplest case, wanting the steady state phase error to be zero a long time after the a step function pertubation: The key to having a theoretical steady state phase error is to have at least one pure integrator in the loop filter. Here you have a "type 1" system (control theory lingo), where the steady state phase error to a step input is zero.
But things are not that simple. You have a digital system that computes the control voltage needed (with some small truncation error), and feeds that number to a DAC with a finite number of bits of resolution. Inevitably the exact voltage that the VCO needs at any one time will be somewhere between the available two voltages that are one LSB apart. So what will happen is that the phase error will slowly form a sawtooth function, where the phase is too low and the DAC moves up one LSB, and the analog filter in the VCXO ramps up the oscillator's phase vs time. Eventually the phase of the VCXO will become too high, and the DAC will move down one LSB, and the analog filter will ramp the VCXO phase down vs time. This will happen over and over forever, along with any noise perturbations that the pll is trying to clean up.
So 95% of the phase error can be cleaned up with using at least one integrator in the loop filter (the integrator can be arithmetical, like a up/down register, etc). The other 5% will be quantization error.
At higher frequencies, there may be some gate delay variations, transmission line distances, etc, that also add small steady state errors to even a type one system.