You have a 'network latency' of 10ns. What is it that you are calling network latency? Is it insertion delay, i.e., the delay it takes from a clock edge to propagate from root to leaf? Is it external delay?
Then you say the clock skew is 20ps and that is met.
I assume the clock is 1ns means the clock period is 1ns?
If all of that means what I think it means... the values are kind of extreme but possible. With a 10ns insertion delay, process variation alone will cause a target skew that is in the order of 10s of ps.
It sounds like a bad clock tree, maybe it could be buffered better to reduce the insertion delay. I don't know. This question, as posed, is kind of vague.