DE4User
Junior Member level 2
Hi All,
In following attachment, there are two ROMs which implement specific logic functions. In Fig.6.14(b),the upper ROM A is a min-term generator which produce certain combinations of input signals, while the lower ROM B sums up those terms to perform some logic functions. In Fig.6.14(c), it is the corresponding MOS layout.
My question is,I dont think the MOS layout in Fig.6.14(c) implements the correct logic which defined in Fig.6.14(b). Take Q2 for example, if input A is logic '0' and input B is logic '1', MOS transistor at second row first column in ROM A will be opened, as a result the first column line in ROM A will be low which in turn will close the MOS transisor at second row in ROM B.Therefore, O2 will output logic '1'. However, by truth table, Q2 should be logic '0'.
View attachment question.bmp
In following attachment, there are two ROMs which implement specific logic functions. In Fig.6.14(b),the upper ROM A is a min-term generator which produce certain combinations of input signals, while the lower ROM B sums up those terms to perform some logic functions. In Fig.6.14(c), it is the corresponding MOS layout.
My question is,I dont think the MOS layout in Fig.6.14(c) implements the correct logic which defined in Fig.6.14(b). Take Q2 for example, if input A is logic '0' and input B is logic '1', MOS transistor at second row first column in ROM A will be opened, as a result the first column line in ROM A will be low which in turn will close the MOS transisor at second row in ROM B.Therefore, O2 will output logic '1'. However, by truth table, Q2 should be logic '0'.
View attachment question.bmp
