The diagram is worthless, can hardly read it. Besides the only clock I see in the picture is to a single FF for some reset sync block, this shows us nothing about how the clock is used in other parts of the design (or maybe this is the only place you use the clock?).
BTW 1.89 ns is approximately 530 MHz, this is not easy to implement in a Virtex 6. Routing alone is usually around 2 ns of the entire clock period. Unless this design is heavily pipelined (i.e. no more than 1 level of LUTs between FFs) you will likely have timing issues.