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question regarding timing analysis or slack time

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dayana42200

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Hello everyone.

Currently, Im designing a processing element.
This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.

I have problem on the timing analysis.
The is no setup time and hold time reported as shown below.

2020-01-11_18-41-56.png

There is no slack for setup time and hold time.
During synthesis and implementation of the device, the is no warning and error.
Please. Could anyone help me?
 

barry

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Is there actually a signal named “Clk” in your design? Is it driving any logic?
 

dayana42200

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Is there actually a signal named “Clk” in your design? Is it driving any logic?

Yes

Below is my timing constraint

NET "Clk" TNM_NET = "Clk";
TIMESPEC "TS_Clk" = PERIOD "Clk" 1.890 ns HIGH 50%;

and also the RTL diagram

2020-01-12_9-42-23.png
 

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The diagram is worthless, can hardly read it. Besides the only clock I see in the picture is to a single FF for some reset sync block, this shows us nothing about how the clock is used in other parts of the design (or maybe this is the only place you use the clock?).

BTW 1.89 ns is approximately 530 MHz, this is not easy to implement in a Virtex 6. Routing alone is usually around 2 ns of the entire clock period. Unless this design is heavily pipelined (i.e. no more than 1 level of LUTs between FFs) you will likely have timing issues.
 

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