Hi,
have a look on the timing diagrams in section 2.0, here you can see how the gate-output pin reflects the TTL input signal in normal operation.
No, please have a look how the duty cyle is defiend, which has been already suggested in one of your previous
threads. Duty cuycle is the ratio between on-time of your signal and it's time periode in perecent. The time periode would stay constant for 5 kHz (T = 200 µs) and the on-time would increase if you are changing your 2% duty-cycle signal to a higher one i.e. 100%. Here, the frequency stays the same. This constant frequency holds for D < 100 %, as you would not see a signal change for D = 100% (it is a DC signal) if probing the signal with a scope, thus no frequency can be determined. Here, you would formally speak of e.g. 5 kHz & D = 100 %, if you are going to change D during operation (e.g. from 100% to 33%), and an actual frequency (periodic signal change) during operation is present.
BR