noloser
Junior Member level 1
is the "after" operation of VHDL synthesisable into a actual hardware design or it was only be used for simulation modeling? let say, if i write:
a <= b or c after 20ns;
will the synthesised hardware actually update the output after (appx) 20ns after a change in inputs or it will just use the default hardware delay and ignore the "after" operation.
please help me in this as i need to create a delay modeling on my design to meet the timing constraint on the interconnected ICs, so i need a good way to model signal delay with VHDL which actually can be synthesis into a actual hardware.
Thank alot for any help!!!
a <= b or c after 20ns;
will the synthesised hardware actually update the output after (appx) 20ns after a change in inputs or it will just use the default hardware delay and ignore the "after" operation.
please help me in this as i need to create a delay modeling on my design to meet the timing constraint on the interconnected ICs, so i need a good way to model signal delay with VHDL which actually can be synthesis into a actual hardware.
Thank alot for any help!!!