Question regarding delaying signal with FPGA in VHDL?

[noloser]

is the "after" operation of VHDL synthesisable into a actual hardware design or it was only be used for simulation modeling? let say, if i write:
a <= b or c after 20ns;
will the synthesised hardware actually update the output after (appx) 20ns after a change in inputs or it will just use the default hardware delay and ignore the "after" operation.

please help me in this as i need to create a delay modeling on my design to meet the timing constraint on the interconnected ICs, so i need a good way to model signal delay with VHDL which actually can be synthesis into a actual hardware.

Thank alot for any help!!!

 

[Elephantus]

No delay is synthesizable as far as I know. The delay in the implemented design depends on the target chip, and on placement and routing of the design elements within the chip. Delay statements will probably be ignored/discarded at synthesis.

If you need to match the timing spec in real hardware - you will need to add timing constraints into your VHDL code or constraints file. Check with your synthesizer manuals how to specify timing constraints.

 

[noloser]

Thank for your info, at least i won't waste time write a code that end up not working in the hardware. can time constraint be different for different module within a single project?