Oh wait! Verilog could be interpreting it like this, which is legal:
y = a+b++c++d++x;
y = a + b + +c + +d + +x;
y = a + b + (+c) + (+d) + (+x);
y = a + b + c + d + x;
ModelSim (possibly incorrectly) rejects a+b++c++d++x, but the Xilinx XST compiler accepts it as a+b+c+d+x.
Unary '+' is rarely used, and it seems suspicious here. This could be one of those sneaky interview questions. It caught me!
i am agree with echo47,
"+" can also work as unary operator in verilog
And as this unary operator has higher precedence over the binary "+" operator, your expression will work as explained by echo47.