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Question on Verilog operator ++

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feel_on_on

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example: y = a+b++c++d++x;

who can tell me what operator is ++ ?

"++" means what on verilog ?


Thanks
 

echo47

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Question on verilog

That's a syntax error in Verilog. It doesn't have any ++ operator.

SystemVerilog and C provide the ++ increment operator, but it's a unary operator, so the example would still be a syntax error.
 

feel_on_on

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Question on verilog

does verilog-A use "++"? then...simulated with nc-verilog . no error was reported!
 

echo47

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Question on verilog

Oh wait! Verilog could be interpreting it like this, which is legal:
y = a+b++c++d++x;
y = a + b + +c + +d + +x;
y = a + b + (+c) + (+d) + (+x);
y = a + b + c + d + x;

ModelSim (possibly incorrectly) rejects a+b++c++d++x, but the Xilinx XST compiler accepts it as a+b+c+d+x.

Unary '+' is rarely used, and it seems suspicious here. This could be one of those sneaky interview questions. It caught me! :oops:
 

darylz

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Question on verilog

anybody can explain this for me?
y = a+b++c++d++x;
 

rakesh448

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Re: Question on verilog

++ operator in verilog is error, it does not have any such operator

++ supports in C and system verilog
 

bharat_in

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Re: Question on verilog

i am agree with echo47,
"+" can also work as unary operator in verilog
And as this unary operator has higher precedence over the binary "+" operator, your expression will work as explained by echo47.

Good question...
 

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